1. Field of the Invention
This invention relates generally to transistorized logic circuitry and, more particularly, to a circuit for eliminating delays in digital logical circuitry using differential signals.
2. Description of the Related Art
Current-mode logic (CML) gates operating with differential mode signals suffer from an inherent signal delay problem. Upper and lower transistors and transistor pairs are cascoded, with a first differential input logic signal driving the upper level transistors and a second differential input logic signal driving the lower level transistors. The circuit output is connected to the collectors of the upper level transistors. Therefore, a change in the first logic signal is seen at the output with a delay associated with the action of the upper level transistors. Changes in the second input logic signal, however, involve the delays associated with both the upper and lower level transistors.
FIG. 1 is a schematic diagram of a conventional differential signal AND circuit (prior art). The circuit 10 performs an AND logical operation in response to the two input signals A and B. Since A and B are differential signals, they have N (first) and P (second) polarities. Thus, when AP is high, AN is low. Likewise, when BP is high, BN is low. The output of the logical operation is provided as a differential signal CP/CN. As mentioned above, changes in the A differential signals appear at the output with a delay associated with the upper level transistors 12 and 14. However, changes in the BP signal appear at the output with a delay associated with transistors 12, 14, and 16. Since the AND logical operation depends upon combinations of the A and B signals, the output signals are necessarily effected by the delay in the BP signal. These delays can add jitter and distortion to the output signal, and at high speeds of operations may even cause logic errors. Delays also exist in exclusive OR and OR circuitry using differential signals, since the circuit designs are very similar to the AND circuit design of FIG. 1.
It would be advantageous if differential logic circuitry could be designed to operate with minimum delays.
It would be advantageous if differential logic circuitry could be designed to equalize the delays associated with each input signal.
It would be advantageous if differential logic circuitry could be designed to have only a one transistor delay.
Accordingly, in an integrated circuit current-mode logic circuit, a method is provided for supplying a differential output signal with equal delays, the method comprises: accepting a first differential signal and an offset first differential signal with a voltage level offset; accepting a second differential signal and an offset second differential signal with a voltage level offset; performing a first logical operation using the first differential signal and the offset second differential signal; supplying a first operation differential signal product having a first delay associated with the first differential signal and a second delay, greater than the first delay, associated with the offset second differential signal; performing the first logical operation using the second differential signal and the offset first differential signal; supplying a first operation differential signal product having a first delay associated with the second differential signal and a second delay, greater than the first delay, associated with the offset first differential signal; and, combining the supplied first operation differential signal products to supply a combined first operation differential signal product having a first delay.
Also provided is an integrated circuit, CML circuit for supplying a differential output signal with equal delays, the circuit comprises a first differential cascode section having an upper transistor stage to accept a first differential input signal and a lower transistor stage to accept an offset second differential input. A second differential cascode section has an upper transistor stage to accept a second differential input signal and a lower transistor stage to accept an offset first differential input. The offset signals are one diode drop lower in voltage.
The first and second cascode sections are connected to supply a differential output signal having equal delays in response to the first differential input signal, the second differential input signal, the first offset differential input signal, and the second offset differential signal. Specific examples are provided of exclusive OR, OR, and AND circuits. However, the same equal delay principles can be applied to any other logical operation process, such as NAND and NOR logic circuits.